1. Field of the Invention
The present invention relates to memory devices and systems including error correction code (ECC) logic.
2. Description of Related Art
Memory technologies used for integrated circuit memories are being developed at smaller and smaller technology nodes, and are being deployed on larger and larger memory arrays on a single integrated circuit. As the technology for memory cells advances, the margins for sensing the data can become tighter. Also, the ability of the memory cells to hold data values in the presence of disturbance of the memory cell state caused by high speed and high volume accesses to the memory cells and to neighboring memory cells can be limited by the tighter margins.
To address issues like those that arise from tighter margins and memory cell disturbance, as these technologies scale in size and density, use of error correcting codes (ECCs) embedded with integrated circuit memory has become more widespread.
Flash memory is usually configured so that it can be erased a block at a time by a block erase. When a block is erased, memory cells in the block are set to one logic value, such as 0. After a block is erased, memory cells in the block can be programmed to a different value, such as 1. Once a memory cell is programmed to 1, the memory cell can be changed back to 0 by a block erase of the block including the programmed memory cell. Once some memory cells in a block, such as cells in a selected byte or word in the block, are programmed to 1 during a first program operation, other memory cells in a different byte or word in the same block that are known to be in the erased state, can still be programmed to 1 during a second program operation without requiring a pre-erase of the block. A block erase, followed by a first program operation and the second program operation to different locations in the same block can be referred to as double patterning for the purpose of this description. Of course, the block erase operations could be followed by many program operations (more than two) when each program operation is directed to a different part of the block to accomplish a “multiple patterning operation.”
In a double or multiple patterning operations, an error correction code (ECC) can be computed and programmed at a particular location in the block during the first program operation. However, the ECC cannot be changed safely for the second program operation in a memory that relies on block erase. The ECC cannot be safely changed in the second program operation because a re-computed ECC may require changing 1 to 0 for at least one bit in the ECC, and that change could require a block erase that would erase data in the entire block.
It is desirable to provide a solution for reliably controlling utilization of ECC logic for error detection and correction for double patterning and multiple patterning operations.